1. Technical Field
The field of the present invention pertains to electronic circuitry. More particularly, the present invention relates to a method for achieving tight control of transistor characteristics during the production process.
2. Description of Related Art
Photomasks are an integral component in the lithographic process. Photomasks are used as masters to optically transfer images of integrated circuits onto semiconductor wafers. A lightsource is used to project light through the photomask to cast an image of the device's design onto a silicon wafer coated with a light sensitive material. However, manufacturability of designs has become a critical issue as feature sizes have reached and surpassed resolution limits of lithography tools used in wafer production. Semiconductors are being built at the subwavelength level, which can result in problems because the circuit images printed on the silicon wafer are actually smaller than the wavelength of the lightsource used to expose the pattern. Such problems include projection distortion effects and effects neighboring features can have on the final position, shape, and size of a given feature of the projected design.
In order to be able to adequately reproduce designs on silicon wafers, new methods of reticle enhancement have been introduced, such as full chip optical proximity correction (OPC) and other resolution enhancement techniques (RET). While other RET techniques in most cases remain optional, OPC has become an integrated part of the photomask tapeout flow at 0.13 μm technologies and below. The object of OPC is to make systematic modifications to the mask geometry that compensate for distortions introduced by the optical system and the photoresist and etching process. OPC uses the original mask design as an input and introduces some intentional distortions to the feature shapes on the mask in order to compensate for known process distortions during mask and wafer manufacturing. Such compensation, while not perfect, results in improvement of pattern fidelity and linewidth control that could not be achieved otherwise. OPC modifies the photomask by adding structures to the designs and patterns on masks to correct for critical dimension and resolution variations. These modifications enhance the printability of the pattern on the wafer.
Conventional OPC techniques, however, contain several disadvantages. Although OPC significantly improves pattern printability, it has limited accuracy. FIGS. 2A, 2B, and 2C show an example of cell layout transformations that can occur through different steps of the wafer production process. The cell is first shown in its initial design in FIG. 2A with critical areas 205 and 210. The resulting photomask after performance of the OPC process is shown in FIG. 2B, whereby structures are modified in the initial design to correct for dimension and resolution variations. FIG. 2C shows the device after manufacturing and reveals how optical distortions and other process defects can result in distorting rectangles into ovals and line-width variations, even though OPC has been performed. These residual pattern errors have negative impact on device yield and manufacturability.
Residual pattern errors are especially damaging for memories where OPC is expected to enable tight linewidth control in high-density environments. Of particular importance is the variance in parameters between transistors of the same functionality group. FIG. 1 illustrates a plan view of a high-density SRAM Cell. The particular cell layout and transistor assignment shown, for example purposes, is an LSI High Density 6 Transistor (6T) SRAM (Static Random Access Memory) for system-on-chip in 130 nm technology, otherwise known as a 1.87 sq. μm SRAM cell. Cell 100 contains six transistors and three functionality groups. Transistors 115 and 120 perform a pullup function, transistors 125 and 130 perform a pulldown function, and transistors 135 and 140 are passgate transistors. It is crucial, for the SRAM cell performance and functionality, to have an excellent match between transistor parameters within the same functionality group. In FIG. 1, critical area A 145 and critical area B 150 are within the same functionality group and require symmetry between the transistors.
Asymmetry between grouped transistors leads to yield loss and increased marginality of operation at low voltages. For example, automated OPC processes as implemented in the 130 nm logic technology led to symmetry issues within 1.87 sq.μm SRAM cell. Using the 1.87 sq.μm SRAM cell for illustration purposes, close up plan views of critical areas of the wafer pattern as shown in FIGS. 3A, 3B, and 3C demonstrate how the OPC process may induce asymmetry into the memory cell. FIG. 3A depicts the initial design of the cell, where left transistor in critical area A 310 and right transistor in critical area B 320 of the cell are drawn with the same dimensions. In the layout after OPC has been performed, FIG. 3B shows there is a clear difference in the line-width patterns of left transistor 330 and right transistor 340. Left transistor 350 and right transistor 360 of the resulting manufactured wafer as shown in FIG. 3C consequently contain differences in the line-width patterns between the transistors.
Different environments can also affect the final position, shape, and size of the resulting transistor features. For example, OPC-induced asymmetry within the 6 Transistor SRAM cell has occurred due to a slight redesign of poly layout in an area away from transistors in order to ease the task of ILD (interlayer dielectric) fill. The redesign unexpectedly led to cell asymmetry due to reduction of linewidth, a lower transistor threshold voltage, and higher drive current of the left pulldown transistor. FIGS. 4A–C provide an example, using a 6 transistor SRAM cell (1.87 sq.μm SRAM) for illustration purposes, of how slight modifications of the cell layout can lead to degradation of functionality group symmetry.
FIG. 4A shows two cell layouts, solid line layout 400 and dotted line layout 410, one imposed over the other. Design modifications were made only to solid line layout 400. FIG. 4C illustrates the desired result of the OPC process—symmetric transistors in the same functionality group. In contrast, FIG. 4B illustrates the negative effect small design changes to non-critical poly features in solid line layout 400 in FIG. 4A have on other neighboring features in the cell. The design changes cause asymmetry between the transistors in the functionality group, such that after the OPC process has been performed, the length of left pulldown transistor 420 is different from right pulldown transistor 430. As a result, there is a difference in the transistors' drive current. Conventional OPC processes contain weaknesses since fidelity of transistors may be sacrificed, due to very small changes in surrounding areas, to satisfy the fidelity of other non-critical poly features.
Existing methods to deal with correcting optical distortions in the manufacturing process include performing multiple iterations of fine OPC tuning and multiple (up to 8–10) re-tapeouts of the poly mask, and applying manual OPC to SRAM cells and automated OPC to the rest of the chip. However, the existing methods described above contain several disadvantages. Performing multiple iterations of fine OPC tuning and multiple re-tapeouts of the poly mask is expensive and has a long cycle time to complete each iteration of improvement. Applying manual OPC to SRAM cells and automated OPC to the rest of the chip is not acceptable for system on the chip products using embedded memories, because manual OPC could cause a mismatch between linewidth within logic and memory areas.
Therefore, a need exists for improving the manufacturability of subwavelength optical lithography systems. Specifically, a need exists for enhancing the effectiveness of the OPC process in order to assert better control over transistor parameters.